This invention relates to a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) reduced in cell size and, in particular, to a MOSFET (UMOSFET) with a gate electrode formed in a U-shaped trench and a method of producing the same.
An orthogonal field effect transistor (MOSFET) is a device used in the field of power electronics. Depending upon an apparatus to which the vertical MOSFET is applied, a breakdown voltage (drain-source breakdown voltage: BVdss) between several tens to several hundreds of volts (V) is required. In addition, there is technical trend towards low power consumption by reducing an on-resistance (Ron) during an on-period (during operation), high-speed operation by reducing a parasitic capacitance and a parasitic resistance, improvement of breakdown resistance in a severe operation environment, and improvement of trade-off among these characteristics.
In order to reduce the on-resistance while maintaining a breakdown voltage of a required level, it is necessary to reduce each resistance component in a vertical MOSFET structure. In case of an existing N-channel double-diffusion MOSFET (DMOSFET), resistance components of the on-resistance Ron are given by Equation (1) as described on page 368 in “Power Semiconductor Devices” (written by B. JAYANT BALIGA and published by PWS Publish Company, 1996).Ron=R(N+)+R(CH)+R(A)+R(J)+R(D)+R(S),  (1)where R(N+) represents the resistance component in an N+ source layer, R(CH), in a channel region, R(A), in an accumulation layer, R(J), in a parasitic junction FET region, R(D), in a drain drift layer, and R(S), in a silicon substrate region. However, it is known that R(N+) and R(A) make small contribution as compared with the remaining resistance components.
In recent years, a MOSFET (UMOSFET) with a gate electrode formed in a U-shaped trench is increasingly commercialized because the on-resistance is further reduced as compared with the existing DMOSFET. In the UMOSFET, R(J) is not present in its structure. Equation (1) is rewritten into Equation (2) only with significant terms.Ron≈R(CH)+R(D)+R(S).  (2)
In fact, a source Al (aluminum) resistance depending upon a chip layout and a bonding wire resistance upon mounting are present at a product level. However, in comparison of performance standardized or normalized at a chip level, discussion is often made about those components in Equation (2).
Description will now be made of techniques for reducing the respective resistance components. R(CH) can be reduced by miniaturizing MOSFET cells connected in parallel to improve a current density per unit area. R(D) can be reduced in the following manner. Generally, an epitaxial layer grown on a silicon substrate is used as a drift layer. Therefore, R(D) can be reduced by reducing the thickness of the epitaxial layer or by increasing an impurity concentration. At the same time, however, it is essential to provide a measure for maintaining a breakdown voltage. R(S) can be reduced by reducing the thickness of the silicon substrate or by increasing the impurity concentration. In an application field relatively high in working voltage (for example, 100V or more), the ratio of R(D) is very high. On the other hand, in an application field relatively low in working voltage (for example, 100V or less), R(CH) and R(D) are predominant. At a yet lower working voltage, the ratio of R(CH) is greatest.
Various structures and processes have been proposed for miniaturization of the cells, which is a technique for mainly reducing R(CH) among the above-mentioned resistance components. For example, a technique is proposed for realizing a cell pitch of 3 to 4 μm (Satoshi Matsumoto et al, “A high-performance self-aligned UMOSFET with a vertical trench constant structure”, IEEE Transaction on Electron Devices, Vol. 41, No. 5, pages 814-818, May 1994). Specifically, in addition to a UMOSFET structure with a gate electrode formed in a trench, another trench is formed in a source diffusion layer and filled with W (tungsten) to provide a source contact structure. Description will hereinafter be made of one example of the UMOSFET structure utilizing the above-mentioned technique with reference to FIG. 1.
Referring to FIG. 1, on one surface of an N+-type silicon substrate 401, an N−-type epitaxial layer 402 is formed. On a surface of the N−-type epitaxial layer 402, a P-type base layer 409 and an N+-type source layer 410 are successively formed. In each of trenches reaching the N−-type epitaxial layer 402 through the P-type base layer 409, a gate oxide film 407 and a polysilicon 408 are filled. On the polysilicon 408 to serve as gate electrodes or trench gates, an oxide film 411 is formed by local oxidization of silicon (LOCOS). Between the trench gates, a contact hole 412 is formed to reach the P-type base layer 409 through the N+-type source layer 410. Directly under the contact hole 412, a P+-type base contact layer 414 is formed. Inside the contact hole 412, W 417 is filled by local or selective CVD (chemical vapor deposition). On the oxide film 411 and W 417, a source electrode 418 of Al is formed. On the other surface of the N+-type silicon substrate 401, a Cr—Ni—Ag (chromium-nickel-silver) drain electrode 419 is formed.
The above-mentioned structure is advantageous in the following respects. A source contact region can be determined by LOCOS self-alignment. Furthermore, the P+-type base contact layer 414 can be formed by self-alignment with the contact region. Therefore, a photolithography process requiring two masking steps is unnecessary. Thus, a space between the trench gate and the contact can be designed without considering pattern displacement. As a consequence, it is possible to miniaturize the cell. It is also possible to narrow the contact width by filling W. On the other hand, the above-mentioned structure is disadvantageous in the following respects. Actually, the polysilicon and the gate oxide film in the trench have irregularities left on their surfaces. It is therefore difficult to form the oxide film by LOCOS or to control the thickness of the oxide film, Generally, bird's beak in LOCOS has a length substantially equivalent to the thickness. Therefore, restriction is imposed upon the space between the trench gate and the contact. In addition, the local CVD of W requires an underlying pattern of Ti (titanium), Mo (molybdenum), or the like. In order to form the underlying pattern, the photolithography process is required.
On the other hand, a structure is disclosed in which aluminum is filled by a high-temperature process (up to 500° C.) in a source contact region of a UMOSFET similar to that mentioned above (Akihiko Osawa et al, “2.5V-driven Nch 3rd generation trench gate MOSFET,” Proceedings of International Symposium on Power Semiconductor Devices and ICs, pages 209-212, 1999). In this structure, the cell pitch is reduced to ½ as compared with an existing structure. Furthermore, Japanese Unexamined Patent Publication No. 2000-223708 (JP 2000-223708 A) discloses a UMOSFET structure similar to the above-mentioned structure in which aluminum is filled and a method of producing the same. The UMOSFET structure utilizing the above-mentioned technique will hereinafter be described with reference to FIG. 2.
Referring to FIG. 2, on one surface of an N+-type silicon substrate 501, an N−-type epitaxial layer 502 is formed. On a surface of the N−-type epitaxial layer 502, a P-type base layer 509 and an N+-type source layer 510 are successively formed. In each of trenches reaching the N−-type epitaxial layer 502 through the P-type base layer 509, a gate oxide film 507 and a polysilicon 508 are filled. On the polysilicon 508 to serve as gate electrodes or trench gates, an interlayer oxide film 511 is formed. Between the trench gates, a contact hole 512 is formed to reach the P-type base layer 509 through the N+-type source layer 510. Directly under the contact hole 512, a P+-type base contact layer 514 is formed. Inside the contact hole 512, TiW (titanium tungsten) 56 is deposited to extend onto the interlayer oxide film 511. On the TiW 516, a source electrode 518 of Al is formed, On the other surface of the N+-type silicon substrate 501, a drain electrode 519 is formed.
The above-mentioned structure is advantageous in the following respects. It is possible to obtain the contact with the N+-type source layer 510 at a side wall of the contact hole 512 and to obtain the contact with the P+-type base contact layer 514, i.e., with the P-type base layer 509, at a bottom of the contact hole 512. Therefore, a photolithography process of forming the P+-type base contact layer 514 is unnecessary. However, the above-mentioned structure is disadvantageous in the following respects. In case where the high-temperature process is used to form Al, a special process is required. In addition, in case of typical Al sputtering at a temperature of 100 to 300° C., the coverage is inferior. If a contact hole is small, a void is produced and the contact hole can not sufficiently be filled. As a consequence, restriction is imposed upon a design of the contact width. Even if the contact hole is filled, a surface profile becomes irregular when the Al coverage is inferior. Therefore, a source Al resistance depending upon the chip layout may possibly be increased.
As described in the foregoing, the structures in FIGS. 1 and 2 have some advantages but yet have the above-mentioned disadvantages. Furthermore, there is another disadvantage in common to both of the structures. Specifically, when the P+-type contact layer is formed at the bottom of the contact hole, the impurity concentration in a channel region is increased by lateral or horizontal diffusion. Therefore, a threshold voltage (Vt) is increased. In order to prevent the increase of Vt, it is necessary to widen the space between the trench gate and the contact. As a consequence, miniaturization of the cell can not be achieved. Since the contact with the N+-type source layer is obtained at the side wall of the contact hole, the contact resistance may possibly be increased because the impurity concentration is lowered at the side wall than at the top. In other words, R(N+) small in contribution as compared with the remaining resistance components as described in conjunction with Equation (1) can not negligible. This results in an increase of Ron.